1. Field of the Invention
The invention relates to a process for patterning a substrate, and more particularly for introducing structures which have different dimensions, in particular with regard to the depth, into a substrate
2. Background Information
Structures with different dimensions, in particular with regard to the depth in a substrate, are very often used in Very Large Scale Integration (VLSI) technology, such as in the context of multilayer metallization.
Two metal or interconnect levels which lie above one another and are separated from one another by an electrically insulating interlayer are electrically connected to one another by contact structures running perpendicular to the levels. The contact structures, which are also referred to as contact holes, are introduced into the insulating interlayer, and are generally filled with a metal and extend from an upper interconnect level to the next interconnect level down.
A process for the structuring of an interconnect level with contact holes which is currently in widespread use is the dual damascene process, in which interconnects and contact holes are introduced into the insulating interlayer as an inlay. In a single damascene process, structures of a certain depth, i.e. interconnect or contact holes, are etched into a substrate, and the etched recesses in the substrate are filled with a material, e.g., metal, in the case of interconnects. Excess material on the surface of the substrate is removed by etching back or a Chemical Mechanical Polishing (CMP) step. The dual damascene process makes it possible for structures with two different depths to be structured in the substrate, for example contact holes and interconnects, as an inlay in the manner described. A dual damascene process requires two lithography levels, each having a mask which is to be imaged onto the substrate and includes the arrangement of the structures, one mask predetermining the arrangement of the shallower structure, e.g., interconnects, and the other mask predetermining the arrangement of the deeper structure, e.g., contact holes.
The structuring of the substrate for a dual damascene process for the introduction of interconnects and contact holes into the substrate is roughly outlined in FIGS. 1A–F. Substrate 4 is provided with a photosensitive layer 1 (FIG. 1A), onto which a mask 14 (FIG 1B), which includes an interconnect arrangement, is then imaged by means of a lithography step. After patterning of photosensitive layer 1, during which step photosensitive layer 1 is partially opened and substrate 4 becomes visible in the openings 10 (FIG. 1C), the trenches 11 for the interconnects are etched into substrate 4 down to a predetermined depth, as depicted in FIG. 1D. Photosensitive layer 1 is removed and replaced with a new photosensitive layer 1′, illustrated in FIG. 1E. Mask 15, which includes a contact hole arrangement, is imaged onto the new photosensitive layer 1′ in a second lithography step (FIG. 1F). After photosensitive layer 1′ has been patterned (FIG. 1G), deep trenches for the contact holes 12 are etched into substrate 4 (FIG. 1H). Finally, all the structures in the substrate 4 are filled with metal, and excess metal on the surface of the substrate 4 is removed (not shown).
The processing order can also be reversed, i.e. structuring of the contact holes can be performed first, followed by structuring of the interconnects. In any event, the introduction of structures with two different depths requires two lithography levels which have to be precisely matched to one another. On the one hand, the two mask layouts have to fit one another, and on the other hand they have to be highly accurately imaged onto one another, with even the slightest misalignment in the two layouts making the entire structuring unusable. When the second mask plane is being aligned with respect to the first, the coverage accuracy of the exposure unit constitutes an obstacle, i.e. the quality of alignment of the two mask levels with respect to one another is limited. The lack of error tolerance with regard to the relative alignment of the two levels leads to a reduction in production yield, which in turn increases the costs of VLSI products.
It will therefore be appreciated that a need exists to develop a better process for introducing a plurality of structures which include structures of different depth into a substrate.